Method for efficient localized self-heating analysis using location based deltat analysis

ABSTRACT

Aspects of the present invention include a method, system and computer program product that provides for improved localized self-heating analysis during IC design. The method includes a processor for modeling a power characteristic and a thermal resistance characteristic for each one of a plurality of locations within a cell that is being designed into an integrated circuit; for performing a self-heating analysis to determine an amount of heat at each one of the plurality of locations within the cell; and for creating a thermal profile for the cell, wherein the thermal profile includes a maximum self-heating value for each of the plurality of locations within the cell and includes an average self-heating value for the cell, and wherein the maximum self-heating value and the average self-heating value are derived from the determined amount of heat at each one of the plurality of locations within the cell.

BACKGROUND

The present invention relates to the design of integrated circuits(ICs), and more specifically, to a method, system and computer programproduct that provides for improved localized self-heating analysisduring IC design primarily at the gate level.

In the normal operation of ICs, it is known that the switching oftransistors designed into the IC consumes electrical power, whichgenerates heat that causes a rise in the temperature at variouslocations (“hot spots”) within the IC. This is commonly known asself-heating or DeltaT (i.e., temperature change).

Transistors are one of the basic building blocks of design elements orcells (e.g., an inverter, a NAND gate, a latch, etc.) within a typicalIC. A single cell may comprise a relatively large number of transistorsand other building blocks (e.g., resistors, capacitors, etc.), dependingon the specific functionality of that type of cell. A designer of an ICtypically may have a library of hundreds or even a thousand or morecells from which to choose when designing the various macro functions ofa particular IC.

The increased temperature of the IC at certain locations may impactand/or cause, for example, leakage currents, circuit delays, circuitfunctionality, and both front end of the line (FEOL) and back end of theline (BEOL) IC fabrication reliability. Thus, it is desirable whendesigning an IC to perform an analysis of the progressing IC design toaccurately identify localized hot spots in the design and revise the ICdesign to correct for these hot spots (i.e., to better dissipate theheat through the various devices formed in the IC along with the wiresand substrate).

What is needed is an improved method for analysis of localizedself-heating within an IC during the gate design phase, wherein theanalysis accurately captures the heterogeneity of the self-heating orDeltaT within a cell of the IC in a relatively rapid and efficient“in-context” manner and relatively early in the IC gate level designflow process.

SUMMARY

According to one or more embodiments of the present invention, acomputer-implemented method of fabricating a semiconductor deviceincludes modeling, by a processor, a power characteristic and a thermalresistance characteristic for each one of a plurality of locationswithin a cell that is being designed into an integrated circuit;performing, by the processor, a self-heating analysis to determine anamount of heat at each one of the plurality of locations within the cellthat is being designed into the integrated circuit; and for creating, bythe processor, a thermal profile for the cell that is being designedinto the integrated circuit, wherein the thermal profile includes amaximum self-heating value for each of the plurality of locations withinthe cell that is being designed into the integrated circuit and includesan average self-heating value for the cell that is being designed intothe integrated circuit, and wherein the maximum self-heating value andthe average self-heating value are derived from the determined amount ofheat at each one of the plurality of locations within the cell.

According to another embodiment of the present invention, a systemincludes a processor in communication with one or more types of memory,the processor configured to perform a method of fabricating asemiconductor device in which the processor is configured to model apower characteristic and a thermal resistance characteristic for eachone of a plurality of locations within a cell that is being designedinto an integrated circuit; to perform a self-heating analysis todetermine an amount of heat at each one of the plurality of locationswithin the cell that is being designed into the integrated circuit; andto create a thermal profile for the cell that is being designed into theintegrated circuit, wherein the thermal profile includes a maximumself-heating value for each of the plurality of locations within thecell that is being designed into the integrated circuit and includes anaverage self-heating value for the cell that is being designed into theintegrated circuit, and wherein the maximum self-heating value and theaverage self-heating value are derived from the determined amount ofheat at each one of the plurality of locations within the cell.

According to yet another embodiment of the present invention, a computerprogram product includes a storage medium readable by a processingcircuit and storing instructions for execution by the processing circuitfor performing a method of fabricating a semiconductor device thatincludes modeling a power characteristic and a thermal resistancecharacteristic for each one of a plurality of locations within a cellthat is being designed into an integrated circuit; performing aself-heating analysis to determine an amount of heat at each one of theplurality of locations within the cell that is being designed into theintegrated circuit; and creating a thermal profile for the cell that isbeing designed into the integrated circuit, wherein the thermal profileincludes a maximum self-heating value for each of the plurality oflocations within the cell that is being designed into the integratedcircuit and includes an average self-heating value for the cell that isbeing designed into the integrated circuit, and wherein the maximumself-heating value and the average self-heating value are derived fromthe determined amount of heat at each one of the plurality of locationswithin the cell.

Additional features and advantages are realized through the techniquesof the present invention. Other embodiments and aspects of the inventionare described in detail herein and are considered a part of the claimedinvention. For a better understanding of the invention with theadvantages and the features, refer to the description and to thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The forgoing and other features, and advantages ofthe invention are apparent from the following detailed description takenin conjunction with the accompanying drawings in which:

FIG. 1 depicts a cloud computing environment according to one or moreembodiments of the present invention;

FIG. 2 depicts abstraction model layers according to one or moreembodiments of the present invention;

FIG. 3 is a block diagram illustrating one example of a processingsystem for practice of the teachings herein;

FIG. 4 is a flow diagram of a method for analysis of localizedself-heating within an IC during the gate level design phase inaccordance with one or more embodiments of the present invention;

FIG. 5 is a more detailed flow diagram of a particular portion of themethod of the flow diagram of FIG. 4 in accordance with one or moreembodiments of the present invention;

FIG. 6 is a more detailed flow diagram of the particular portion of theflow diagram of FIG. 5, which is a portion of the method of the flowdiagram of FIG. 4, in accordance with one or more embodiments of thepresent invention;

FIG. 7 is a more detailed flow diagram of a particular portion of themethod of the flow diagram of FIG. 4 in accordance with one or moreembodiments of the present invention; and

FIG. 8 is a visual illustration of various cell parameters determined bythe method of the flow diagrams of FIGS. 4-7 as a result of the analysisof localized self-heating within an IC in accordance with one or moreembodiments of the present invention.

DETAILED DESCRIPTION

It is understood in advance that although this disclosure includes adetailed description on cloud computing, implementation of the teachingsrecited herein are not limited to a cloud computing environment. Rather,embodiments of the present invention are capable of being implemented inconjunction with any other type of computing environment now known orlater developed.

Cloud computing is a model of service delivery for enabling convenient,on-demand network access to a shared pool of configurable computingresources (e.g. networks, network bandwidth, servers, processing,memory, storage, applications, virtual machines, and services) that canbe rapidly provisioned and released with minimal management effort orinteraction with a provider of the service. This cloud model may includeat least five characteristics, at least three service models, and atleast four deployment models.

Characteristics are as follows:

On-demand self-service: a cloud consumer can unilaterally provisioncomputing capabilities, such as server time and network storage, asneeded automatically without requiring human interaction with theservice's provider.

Broad network access: capabilities are available over a network andaccessed through standard mechanisms that promote use by heterogeneousthin or thick client platforms (e.g., mobile phones, laptops, and PDAs).

Resource pooling: the provider's computing resources are pooled to servemultiple consumers using a multi-tenant model, with different physicaland virtual resources dynamically assigned and reassigned according todemand. There is a sense of location independence in that the consumergenerally has no control or knowledge over the exact location of theprovided resources but may be able to specify location at a higher levelof abstraction (e.g., country, state, or datacenter).

Rapid elasticity: capabilities can be rapidly and elasticallyprovisioned, in some cases automatically, to quickly scale out andrapidly released to quickly scale in. To the consumer, the capabilitiesavailable for provisioning often appear to be unlimited and can bepurchased in any quantity at any time.

Measured service: cloud systems automatically control and optimizeresource use by leveraging a metering capability at some level ofabstraction appropriate to the type of service (e.g., storage,processing, bandwidth, and active user accounts). Resource usage can bemonitored, controlled, and reported providing transparency for both theprovider and consumer of the utilized service.

Service Models are as follows:

Software as a Service (SaaS): the capability provided to the consumer isto use the provider's applications running on a cloud infrastructure.The applications are accessible from various client devices through athin client interface such as a web browser (e.g., web-based e-mail).The consumer does not manage or control the underlying cloudinfrastructure including network, servers, operating systems, storage,or even individual application capabilities, with the possible exceptionof limited user-specific application configuration settings.

Platform as a Service (PaaS): the capability provided to the consumer isto deploy onto the cloud infrastructure consumer-created or acquiredapplications created using programming languages and tools supported bythe provider. The consumer does not manage or control the underlyingcloud infrastructure including networks, servers, operating systems, orstorage, but has control over the deployed applications and possiblyapplication hosting environment configurations.

Infrastructure as a Service (IaaS): the capability provided to theconsumer is to provision processing, storage, networks, and otherfundamental computing resources where the consumer is able to deploy andrun arbitrary software, which can include operating systems andapplications. The consumer does not manage or control the underlyingcloud infrastructure but has control over operating systems, storage,deployed applications, and possibly limited control of select networkingcomponents (e.g., host firewalls).

Deployment Models are as follows:

Private cloud: the cloud infrastructure is operated solely for anorganization. It may be managed by the organization or a third party andmay exist on-premises or off-premises.

Community cloud: the cloud infrastructure is shared by severalorganizations and supports a specific community that has shared concerns(e.g., mission, security requirements, policy, and complianceconsiderations). It may be managed by the organizations or a third partyand may exist on-premises or off-premises.

Public cloud: the cloud infrastructure is made available to the generalpublic or a large industry group and is owned by an organization sellingcloud services.

Hybrid cloud: the cloud infrastructure is a composition of two or moreclouds (private, community, or public) that remain unique entities butare bound together by standardized or proprietary technology thatenables data and application portability (e.g., cloud bursting forload-balancing between clouds).

A cloud computing environment is service oriented with a focus onstatelessness, low coupling, modularity, and semantic interoperability.At the heart of cloud computing is an infrastructure comprising anetwork of interconnected nodes.

Referring now to FIG. 1, illustrative cloud computing environment 50 isdepicted. As shown, cloud computing environment 50 comprises one or morecloud computing nodes 10 with which local computing devices used bycloud consumers, such as, for example, personal digital assistant (PDA)or cellular telephone 54A, desktop computer 54B, laptop computer 54C,and/or automobile computer system 54N may communicate. Nodes 10 maycommunicate with one another. They may be grouped (not shown) physicallyor virtually, in one or more networks, such as Private, Community,Public, or Hybrid clouds as described hereinabove, or a combinationthereof. This allows cloud computing environment 50 to offerinfrastructure, platforms and/or software as services for which a cloudconsumer does not need to maintain resources on a local computingdevice. It is understood that the types of computing devices 54A-N shownin FIG. 1 are intended to be illustrative only and that computing nodes10 and cloud computing environment 50 can communicate with any type ofcomputerized device over any type of network and/or network addressableconnection (e.g., using a web browser).

Referring now to FIG. 2, a set of functional abstraction layers providedby cloud computing environment 50 (FIG. 1) is shown. It should beunderstood in advance that the components, layers, and functions shownin FIG. 2 are intended to be illustrative only and embodiments of theinvention are not limited thereto. As depicted, the following layers andcorresponding functions are provided:

Hardware and software layer 60 includes hardware and softwarecomponents. Examples of hardware components include: mainframes 61; RISC(Reduced Instruction Set Computer) architecture based servers 62;servers 63; blade servers 64; storage devices 65; and networks andnetworking components 66. In some embodiments, software componentsinclude network application server software 67 and database software 68.

Virtualization layer 70 provides an abstraction layer from which thefollowing examples of virtual entities may be provided: virtual servers71; virtual storage 72; virtual networks 73, including virtual privatenetworks; virtual applications and operating systems 74; and virtualclients 75.

In one example, management layer 80 may provide the functions describedbelow. Resource provisioning 81 provides dynamic procurement ofcomputing resources and other resources that are utilized to performtasks within the cloud computing environment. Metering and Pricing 82provide cost tracking as resources are utilized within the cloudcomputing environment, and billing or invoicing for consumption of theseresources. In one example, these resources may comprise applicationsoftware licenses. Security provides identity verification for cloudconsumers and tasks, as well as protection for data and other resources.User portal 83 provides access to the cloud computing environment forconsumers and system administrators. Service level management 84provides cloud computing resource allocation and management such thatrequired service levels are met. Service Level Agreement (SLA) planningand fulfillment 85 provides pre-arrangement for, and procurement of,cloud computing resources for which a future requirement is anticipatedin accordance with an SLA.

Workloads layer 90 provides examples of functionality for which thecloud computing environment may be utilized. Examples of workloads andfunctions which may be provided from this layer include: mapping andnavigation 91; software development and lifecycle management 92; virtualclassroom education delivery 93; data analytics processing 94;transaction processing 95; and a method 96 that provides for improvedlocalized self-heating analysis during IC design primarily at the gatelevel in accordance with one or more embodiments of the presentinvention.

Referring to FIG. 3, there is shown a processing system 100 forimplementing the teachings herein according to one or more embodiments.The system 100 has one or more central processing units (processors) 101a, 101 b, 101 c, etc. (collectively or generically referred to asprocessor(s) 101). In one embodiment, each processor 101 may include areduced instruction set computer (RISC) microprocessor. Processors 101are coupled to system memory 114 and various other components via asystem bus 113. Read only memory (ROM) 102 is coupled to the system bus113 and may include a basic input/output system (BIOS), which controlscertain basic functions of system 100.

FIG. 3 further depicts an input/output (I/O) adapter 107 and a networkadapter 106 coupled to the system bus 113. I/O adapter 107 may be asmall computer system interface (SCSI) adapter that communicates with ahard disk 103 and/or tape storage drive 105 or any other similarcomponent. Hard disk 103 and tape storage device 105 are collectivelyreferred to herein as mass storage 104. Operating system 120 forexecution on the processing system 100 may be stored in mass storage104. A network adapter 106 interconnects bus 113 with an outside network116 enabling data processing system 100 to communicate with other suchsystems. A screen (e.g., a display monitor) 115 is connected to systembus 113 by display adaptor 112, which may include a graphics adapter toimprove the performance of graphics intensive applications and a videocontroller. In one embodiment, adapters 107, 106, and 112 may beconnected to one or more I/O busses that are connected to system bus 113via an intermediate bus bridge (not shown). Suitable I/O buses forconnecting peripheral devices such as hard disk controllers, networkadapters, and graphics adapters typically include common protocols, suchas the Peripheral Component Interconnect (PCI). Additional input/outputdevices are shown as connected to system bus 113 via user interfaceadapter 108. A keyboard 109, mouse 110, and speaker 111 allinterconnected to bus 113 via user interface adapter 108, which mayinclude, for example, a Super I/O chip integrating multiple deviceadapters into a single integrated circuit.

In exemplary embodiments, the processing system 100 includes a graphicsprocessing unit 130. Graphics processing unit 130 is a specializedelectronic circuit designed to manipulate and alter memory to acceleratethe creation of images in a frame buffer intended for output to adisplay. In general, graphics processing unit 130 is very efficient atmanipulating computer graphics and image processing, and has a highlyparallel structure that makes it more effective than general-purposeCPUs for algorithms where processing of large blocks of data is done inparallel.

Thus, as configured in FIG. 3, the system 100 includes processingcapability in the form of processors 101, storage capability includingsystem memory 114 and mass storage 104, input means such as keyboard 109and mouse 110, and output capability including speaker 111 and display115. In one embodiment, a portion of system memory 114 and mass storage104 collectively store an operating system to coordinate the functionsof the various components shown in FIG. 3.

In accordance with one or more embodiments of the present invention,methods, systems, and computer program products are disclosed thatprovide for improved localized self-heating analysis during IC designprimarily at the gate level.

Referring to FIG. 4, there illustrated is a flow diagram of a method 300according to one or more embodiments of the present invention thatprovides for improved localized self-heating analysis during IC designprimarily at the gate level, wherein the analysis accurately capturesthe heterogeneity of the self-heating or DeltaT within a cell of the ICin a relatively rapid and efficient “in-context” manner and relativelyearly in the IC gate level design flow process. As used herein, the“heterogeneity” of the self-heating or DeltaT of a cell refers to theoverall self-heating or DeltaT value for a cell as typically beingcomprised of potentially widely varying values for temperature atdifferent (transistor) locations within a single cell.

The in-context cell DeltaT analysis according to embodiments of thepresent invention is advantageous in that it captures any dependency ofthe localized self-heating or DeltaT on the workload of the cell beinganalyzed along with the dependency of the localized self-heating on theexternal load placed on the cell being analyzed. The workload iscommonly considered to be the activity (e.g., transistor switching) ofthe particular cell being analyzed (e.g., a NAND gate). In turn, theexternal load placed on the particular cell being analyzed is commonlyconsidered to be the load (e.g., capacitance) that the cell is driving.The localized self-heating or DeltaT of any cell within the IC isinherently dependent on the workload of the cell and the external loadof the cell, among other factors. It follows that by reducing theworkload of the cell and/or the load on the cell (e.g., by making designchanges to the IC at the gate level), the localized self-heating orDeltaT can be reduced. This can be carried out by changing or selectingdifferent cells from within a library of “standard” cells to be placedwithin the IC design instead of changing the structure of any one ormore cells themselves.

Further, the workload and the external load can each vary relativelywidely among various locations (e.g., x, y coordinates of transistorswithin a cell) in a cell depending upon where the cell is located andutilized in the overall functional design of the IC. As such, thecorresponding temperatures associated with the various locations withina cell can also vary relatively widely. Thus, it is advantageous thatthe analysis of the self-heating of each cell be performed on alocalized, “in-context” basis, as is with embodiments of the presentinvention. Further, the heterogeneity of the self-heating or DeltaT ofthe cell captures the overall self-heating or DeltaT value for thatcell.

Modern ICs are typically designed in a hierarchical manner. For example,there may be an upper unit level in the IC design process, followed by alower, more detailed gate level design process, which itself is followedby an even lower and more detailed transistor level design process.Embodiments of the present invention are primarily concerned with (butnot necessarily limited to) the gate level of the IC design process.

In one or more embodiments of the present invention, the method 300 maybe embodied in software that is executed by computer elements locatedwithin a network that may reside in the cloud, such as the cloudcomputing environment 50 described hereinabove and illustrated in FIGS.1 and 2. In other embodiments, the computer elements may reside on acomputer system or processing system, such as the processing system 100described hereinabove and illustrated in FIG. 3, or in some other typeof computing or processing environment now known or hereinafter created.

In the method 300 of the flow diagram of FIG. 4, an operation in block304 models the cell power and thermal resistance on a per location basiswithin each cell in the library of cells. This operation 304 produces aparameterized model for each cell or location with each cell. Asdiscussed above, each location within a cell may comprise the x, ycoordinates of one or more transistors within a cell, or the locationmay represent the x, y coordinates of the entire cell itself. Also,there may be hundreds or even a thousand or more cells in the library ofcells. As such, this modeling operation 304 may be carried out for eachone of the cells in the library of cells in accordance with embodimentsof the present invention. In the alternative, the modeling operation 304may be carried out for those cells that are likely to be used during thedesign of the IC, which results in a relatively smaller number of cells(e.g., 50) being modeled in this operation 304.

According to embodiments of the present invention, this modelingoperation 304 may be performed “off line” in a transistor level modelingphase 308 of the overall IC design process (that is, not during theprimary gate level design operations of the IC design process and notduring the “analysis” operations of embodiments of the presentinvention). Also, the various operations that comprise this modelingoperation 304 are described and illustrated in more detail hereinafterin conjunction with the flow diagrams of FIGS. 5 and 6.

In contrast, the remaining operations in blocks 312 and 316 may beperformed in a gate level design and analysis phase 320 of the overallIC design process. The operation in block 312 comprises performing aself-heating or DeltaT (DT) analysis on a per location basis within eachcell. In turn, the operation in block 316 comprises mapping a locationwithin a cell to other information and creating quick cell thermalprofiles, max-DT values, and average-DT values. The more detailedoperations that comprise these operations 312, 316 are described andillustrated in greater detail hereinafter in conjunction with the flowdiagram of FIG. 7.

Referring to FIG. 5, there illustrated is a more detailed flow diagramof the modeling operation in block 304 of the method 300 of the flowdiagram of FIG. 4 in accordance with one or more embodiments of thepresent invention. In an operation in block 330, a particular one of themany cells in the library is loaded or selected for use by the ICdesigner. Specifically, the IC designer has access to the transistorlevel design of the selected cell.

In an operation in block 334, the location based thermal resistance RTHof the selected cell is modeled. The thermal resistance value may becharacterized by computing or determining the effective thermalresistance from the schematic or layout of the selected standard celland considering the topology of the cell and, for example, thetransistor finger and fin count. More specifically, the thermalresistance value may be determined as a constant (degrees C./Watts)between the IC device temperature increase and the dissipated power.Alternatively, DeltaT equals RTH times Current or Power. That is, DeltaTis proportional to the dissipated power with a proportionality constantof RTH. It follows that the thermal conductivity or thermal conductancevalue, GTH, equals the inverse of the thermal resistance value (i.e.,GTH=1/RTH). The RTH as characterized or modeled may be stored in thepower rule for the selected standard cell.

An operation in block 338 may be run in parallel with the operation inblock 334. The operation 338 may model the location based AC power andthe leakage cell power for the selected cell.

Following the operations in blocks 334, 338, an operation in block 342may generate the location based cell model. Each one of the plurality ofcells in the library utilized by the IC designer may have a locationbased model generated for itself by this operation in block 342. This isdescribed in more detail with respect to the flow diagram of FIG. 6.Referring to FIG. 6, an operation in block 346 computes or determinesthe conductance value, GTH, for each transistor (e.g., field effecttransistor or FET) in the selected cell. As disclosed hereinabove, GTHequals 1/RTH.

Next, an operation in block 350 obtains or gets the associated locationsfor each FET or transistor and computes or determines the thermalconductance (GTH) weight for each such location. Besides a locationbeing the x, y coordinates of a cell or transistors within a cell, alocation may be considered to be a contact within a cell in whichcurrent flows from a power source into the cell. As such, sometimes alocation is typically referred to as a “CA.”

An operation in block 354 then performs location level GTH accumulationand creates thermal conductance (GTH) elements. The result of thisoperation in block 354 is a generated location based conductance valuefor the selected standard cell. Finally, the generated location levelGTH elements or values are stored in the cell model in an operation inblock 358.

Referring to FIG. 7, there illustrated is a more detailed flow diagramof the DeltaT analysis operation 312 and the mapping operation 316 ofthe method 300 of the flow diagram of FIG. 4 in accordance with one ormore embodiments of the present invention. The operations in the flowdiagram of FIG. 7 basically perform an in-context workload analysis andexternal load analysis of the location based cell model generated in theoperation in block 342 of the flow diagram of FIG. 5.

In an operation in block 370, the gate level design is loaded for the ICdesign user. An operation in block 374 identifies cells of interest forlocation based self-heating or DeltaT analysis. This operation may beperformed on all of the cells (e.g., one thousand or more cells) in thelibrary or only on a subset (e.g., 50 cells) of cells of interest in thelibrary. The cells of interest may be selected based on variouscriteria, including, for example, size, complexity, user input, etc.

An operation in block 378 loads the pre-characterized location basedthermal resistance and power contributor models for the selected cellsof interest. These models were determined or generated in the operationin the block 304 of the flow diagram of FIG. 4 as well as the moredetailed flow diagrams of FIGS. 5 and 6. Also provided in this operationin block 378 may be process parameters (e.g., a relatively fasteroperating IC consumes more power and vice versa), voltage parameters(e.g., the operating voltage of the IC), and temperature parameters(e.g., ambient temperature).

An operation in block 382 computes or determines the amount or value ofself-heating or DeltaT for each location in the cell. This may beperformed using the location based thermal resistance and power modelsthat were loaded in the operation in block 378. Next, an operation inblock 386 maps the determined location based DeltaT values to otherinformation in each cell.

Finally, an operation in block 390 creates an in-context cell thermalprofile, computes or determines the max-DeltaT (DT) and average-DTvalues, for example, by looking across all locations within each cell.This type of heterogeneity analysis results in a relatively accuratelocation based thermal profile for the entire (macro) cell. If the ICdesigner utilizing embodiments of the present invention finds any of theinformation regarding the self-heating or DeltaT for a particular cellto be unacceptable (as given by the thermal profile of the cell), thedesigner may perform a re-design of the relevant portion of the IC usinga different one or more cells.

Referring to FIG. 8, there is a visual illustration 400 of various cellparameters determined by the method of the flow diagrams of FIGS. 4-7 asa result of the analysis of localized self-heating within an IC inaccordance with one or more embodiments of the present invention. Thisvisual illustration 400 may be presented to the IC designer on a visualdisplay screen, such as one that is part of one of the computing nodesin the cloud computing environment 50 of FIGS. 1 and 2, or the displaymonitor 115 that is part of the processing system 100 of FIG. 3, or onsome other type of display screen associated with a computing orprocessing environment.

The visual illustration 400 may comprise an illustration of a macro gate404 that contains three cells or cell instances, including a first cell408. As the method of the flow diagrams of FIGS. 4-7 in accordance withembodiments of the present invention is utilized by an IC designer, aDetailed Cell Thermal Profile 412 visual display area is provided. Inthe exemplary embodiment of FIG. 8, the profile is with respect to Cell1. However, each cell may have its profile displayed, typically in turnor in sequence as the analysis of DeltaT proceeds in accordance withembodiments of the present invention on a cell-by-cell basis. Thisdisplay of the profile 412 gives the IC designer the “look and feel” ofthe data and modeling analysis of embodiments of the present invention.

Shown in the visual display area 412 of FIG. 8 are the n number oftransistors or FETs (FETs(1)-FETs(n)), together with the location (e.g.,in x, y coordinates) of each FET within Cell, the thermal resistancevalue (RTH) for each FET at each location, the electrical current value(I) for each FET at each location, and the value of DeltaT for each FETat each location. The value for DeltaT may be determined as the valuefor RTH times the value for I (i.e., DT1=RTH 1×I1). This provides the ICdesigner with detailed information about the self-heating or DeltaT foreach FET within a cell.

The visual illustration 400 may comprise a visual display area 416 thatcomprises a display of various statistics of the DeltaT or self-heatingof Cell 1 (i.e., the current cell being displayed in the visualillustration 400). These statistics may include, for example, theaverage-DT value, the max-DT value, the max-DT at a particular x, ycoordinate value location, and the max-DT of a particular FET. Thesevarious values were computed or determined as disclosed hereinabove.Other self-heating or DeltaT parameter values may be displayed withinthe visual illustration, in light of the teachings herein.

Embodiments of the present invention enable the relatively efficient andaccurate hierarchical self-heating analysis of an IC during the ICdesign process, particularly at the gate level of the design. This isperformed, for example, by capturing the heterogeneity of the DeltaTwithin a cell while performing in-context cell DeltaT analysis. Thein-context cell analysis provides the IC designer with a relatively moredetailed view or picture of the cell being designed. Embodiments arealso performed within acceptable turn-around times during the IC designprocess, due primarily to the relative efficiency of embodiments of thepresent invention. Embodiments also enable the self-heating analysis ofworkload exploration, and enable the efficient DeltaT mitigation oflocalized hot spots early on in the IC design process flow.

In addition, embodiments of the present invention also provide forimproved efficiency in carrying out the DeltaT analysis, as compared toprior art circuit simulator and solver based techniques. That is, it isnot uncommon for such prior art techniques to take hours or even days torun and provide their output analysis with respect to an IC design. Incontrast, embodiments of the present invention may only add no more than5% of the time to the overall IC design process. Thus, the turnaroundtime (or impact percentage) for embodiments of the present invention isvery acceptable within typical IC design techniques.

Further, embodiments of the present invention are scalable, whereasprior art solver based techniques are typically not scalable. Inaddition, embodiments enable in-context workload driven DeltaT analysis,whereas prior art solver based techniques do not. That is, embodimentscapture the heterogeneity of the DeltaT within the cell along with themaximum value of DeltaT within the cell and associated transistors. As aresult, prior art solver based techniques are typically not usable ingate level analysis during the IC design process.

The present invention may be a system, a method, and/or a computerprogram product. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent invention.

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present invention may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions execute entirely on the user's computer,partly on the user's computer, as a stand-alone software package, partlyon the user's computer and partly on a remote computer or entirely onthe remote computer or server. In the latter scenario, the remotecomputer may be connected to the user's computer through any type ofnetwork, including a local area network (LAN) or a wide area network(WAN), or the connection may be made to an external computer (forexample, through the Internet using an Internet Service Provider). Insome embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof instructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

The following definitions and abbreviations are to be used for theinterpretation of the claims and the specification. As used herein, theterms “comprises,” “comprising,” “includes,” “including,” “has,”“having,” “contains” or “containing,” or any other variation thereof,are intended to cover a non-exclusive inclusion. For example, acomposition, a mixture, process, method, article, or apparatus thatcomprises a list of elements is not necessarily limited to only thoseelements but can include other elements not expressly listed or inherentto such composition, mixture, process, method, article, or apparatus.

As used herein, the articles “a” and “an” preceding an element orcomponent are intended to be nonrestrictive regarding the number ofinstances (i.e., occurrences) of the element or component. Therefore,“a” or “an” should be read to include one or at least one, and thesingular word form of the element or component also includes the pluralunless the number is obviously meant to be singular.

As used herein, the terms “invention” or “present invention” arenon-limiting terms and not intended to refer to any single aspect of theparticular invention but encompass all possible aspects as described inthe specification and the claims.

As used herein, the term “about” modifying the quantity of aningredient, component, or reactant of the invention employed refers tovariation in the numerical quantity that can occur, for example, throughtypical measuring and liquid handling procedures used for makingconcentrates or solutions. Furthermore, variation can occur frominadvertent error in measuring procedures, differences in themanufacture, source, or purity of the ingredients employed to make thecompositions or carry out the methods, and the like. In one aspect, theterm “about” means within 10% of the reported numerical value. Inanother aspect, the term “about” means within 5% of the reportednumerical value. Yet, in another aspect, the term “about” means within10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

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 8. A system comprising: a processor incommunication with one or more types of memory, the processor configuredto perform a method of fabricating a semiconductor device in which theprocessor is configured to: model a power characteristic and a thermalresistance characteristic for each one of a plurality of locationswithin a cell that is being designed into an integrated circuit; performa self-heating analysis to determine an amount of heat at each one ofthe plurality of locations within the cell that is being designed intothe integrated circuit; and create a thermal profile for the cell thatis being designed into the integrated circuit, wherein the thermalprofile includes a maximum self-heating value for each of the pluralityof locations within the cell that is being designed into the integratedcircuit and includes an average self-heating value for the cell that isbeing designed into the integrated circuit, and wherein the maximumself-heating value and the average self-heating value are derived fromthe determined amount of heat at each one of the plurality of locationswithin the cell.
 9. The system of claim 8 wherein the processor isconfigured to repeat the model, perform and create steps for each one ofa certain number of cells within a library of cells that are beingdesigned into an integrated circuit.
 10. The system of claim 8 whereineach one of the plurality of locations within a cell that is beingdesigned into an integrated circuit comprises one or more transistors.11. The system of claim 10 wherein the processor configured to model thethermal resistance characteristic comprises the processor configured todetermine a conductance value for each of the one or more transistors.12. The system of claim 8 wherein the processor configured to model apower characteristic and a thermal resistance characteristic comprisesthe processor configured to model a power characteristic and a thermalresistance characteristic offline during a transistor level design phaseof an integrated circuit design process.
 13. The system of claim 8wherein the processor configured to perform a self-heating analysis andto create a thermal profile comprises the processor configured toperform a self-heating analysis and to create a thermal profile during agate level design phase of an integrated circuit design process.
 14. Thesystem of claim 8 the processor further configured to provide a visualdisplay of the power characteristic, the thermal resistancecharacteristic, and the determined amount of heat at each one of theplurality of locations within the cell that is being designed into theintegrated circuit.
 15. A computer program product comprising: a storagemedium readable by a processing circuit and storing instructions forexecution by the processing circuit for performing a method offabricating a semiconductor device comprising: modeling a powercharacteristic and a thermal resistance characteristic for each one of aplurality of locations within a cell that is being designed into anintegrated circuit; performing a self-heating analysis to determine anamount of heat at each one of the plurality of locations within the cellthat is being designed into the integrated circuit; and creating athermal profile for the cell that is being designed into the integratedcircuit, wherein the thermal profile includes a maximum self-heatingvalue for each of the plurality of locations within the cell that isbeing designed into the integrated circuit and includes an averageself-heating value for the cell that is being designed into theintegrated circuit, and wherein the maximum self-heating value and theaverage self-heating value are derived from the determined amount ofheat at each one of the plurality of locations within the cell.
 16. Thecomputer program product of claim 15 wherein the method is repeated foreach one of a certain number of cells within a library of cells that arebeing designed into an integrated circuit.
 17. The computer programproduct of claim 15 wherein each one of the plurality of locationswithin a cell that is being designed into an integrated circuitcomprises one or more transistors.
 18. The computer program product ofclaim 17 wherein modeling the thermal resistance characteristiccomprises determining a conductance value for each of the one or moretransistors.
 19. The computer program product of claim 15 whereinmodeling a power characteristic and a thermal resistance characteristicis performed offline during an transistor level design phase of anintegrated circuit design process.
 20. The computer program product ofclaim 15 wherein performing a self-heating analysis and creating athermal profile are performed during a gate level design phase of anintegrated circuit design process.